1. Field of the Invention
The present invention relates to techniques for handling exceptions in a data processing apparatus, and in particular to a data processing apparatus and method for handling exceptions in situations where multiple instructions can be executed simultaneously in a plurality of pipelined stages of an execution unit.
2. Description of the Prior Art
In a data processing apparatus, it is known to provide one or more dedicated processing units adapted to perform particular processing tasks. For example, a floating point unit may be provided to perform a particular floating point operation, for example a multiply-accumulate operation. Such dedicated processing units may be part of the main processor, or may be provided within a separate coprocessor.
If the operation to be performed by such a dedicated processing unit can be broken down into a number of separate steps, it is common to provide a number of pipelined processing stages within the processing unit. By such an approach, it is possible for a number of instructions to be executed simultaneously within the processing unit. As an instruction is passed into the pipeline, the processing unit will typically retrieve the source data required for the instruction from a data register file, and on completion of the instruction, will store the data result to a predetermined destination register.
When executing such instructions, it is possible that an exception condition may be detected by the processing unit, and in such a situation it is typically necessary to invoke an exception processing tool to deal with the exception, in order to ensure that an appropriate data result is placed in the destination register.
However, in pipelined architectures, the detection of an exception condition may occur later than required to stop the issue of subsequent instructions into the pipeline. Such instructions must be either completed or restarted. A number of prior art techniques have been proposed for dealing with this problem.
Firstly, the problem can be avoided by ensuring that any instruction entering the pipeline which may give rise to an exception condition is completed before any subsequent instruction is allowed to enter the pipeline. Such an approach was employed in the Motorola MC68881 chip, where the CPU was only permitted to issue a subsequent instruction when the current instruction completed.
An alternative approach is to provide a significant area of memory, referred to as a state frame, in which all intermediate states in the pipeline can be stored as and when required. Thus, if an exception condition is detected, and hence the exception processing tool needs to be invoked to recover from the exception, then the state of all stages of the pipeline can be stored in the state frame, such that the pipeline can be restored to its previous state once the exception processing tool has completed the recovery process. Such an approach was employed in the Motorola MC68040 chip. This approach suffers from the drawback that an instruction, when exceptional, blocks completion of all subsequent instructions currently executing in the pipeline. Further, this technique is significantly more complex than the single issue technique discussed previously, and requires significant time to process a store or load of an exceptional state to or from memory.
A further approach employed in prior art processing units involves the use of a history, or reorder, buffer. The reorder buffer typically stores the entire instruction stream of the data processing apparatus, and has logic arranged to send the instructions to the appropriate processing unit(s) of the data processing apparatus, and to subsequently place in the reorder buffer in association with the instruction the data result determined upon execution of that instruction. As each instruction reaches the bottom of the reorder buffer, it is "retired", for example by storing the data result in the appropriate destination register. If, however, an exception condition is associated with the instruction being retired, then the exception processing tool is invoked to recover from the exception. Subsequent to the recovery process, the instruction stream is restarted from the instruction immediately following the retired instruction.
Since exception conditions are quite rare, the reorder buffer can provide good performance, although there is clearly a significant performance hit when an exception does occur, since then all subsequent instructions being executed by all processing units (not just the processing unit handling the exceptional instruction) are re-executed. Further, reorder buffers are of significantly greater complexity and greater chip area than either of the two previously discussed techniques.
It is an object of the present invention to provide a data processing apparatus and method which enables more efficient processing of exception conditions in situations where several instructions may be executed simultaneously within a dedicated processing unit.